The present invention relates generally to analog-to-digital converters, and, more particularly, to analog-to-digital converters capable of operating at very high speeds and suitable for processing signals having high frequency components, such as video signals.
In general, there are a variety of techniques available for conversion of an analog signal to an equivalent digital signal. An analog signal is one that can vary continuously over a range of values and can assume any value within the range, whereas a digital signal takes the form of a numerical quantity representing the value of one of a number of discrete steps in the signal range. The technique best suited for high speed analog-to-digital conversion is known as parallel conversion. In a parallel converter, an input analog signal is simultaneously compared with a number of different reference signals, each corresponding to a discrete step in the signal range. The simultaneous comparison operations are performed in a set of matched comparators. For a zero input signal, for example, all the comparators provide outputs of the same state, and as the input signal increases in value, an increasing number of the comparators provide outputs of the opposite state. In this manner, the analog input signal is quantized, i.e., is recognized as falling between two adjacent discrete levels in the signal range. If an n-bit binary output is required, the input signal is quantized into one of 2.sup.n different quantization levels, utilizing 2.sup.n -1 comparators. Typically, the outputs of the comparators are then processed to provide the desired n-bit binary code equivalent to the instantaneous value of the analog input signal.
For many high speed analog-to-digital conversion applications, the resolution required is equivalent to eight bits or more, and the analog signal must be quantized into 2.sup.8 or 256 discrete levels to attain the desired resolution. This would require 255 matched comparators and approximately 20,000 individual components. Such a device has been manufactured using discrete components, but was found to suffer from a number of significant drawbacks, not the least of which was extremely high cost. The principal disadvantage of such a converter was that the 255 discrete comparator circuits could not always be perfectly matched in their performance characteristics. Futhermore, the input capacitance of the comparators used was relatively high, and a costly buffer amplifier had to be used in many instances. To add further to the cost of such a device using discrete components, differential delays in the converter necessitated use of a sample-and-hold circuit.
Although it might appear that the use of field effect transistors (FET's) in a monolithic circuit would avoid these difficulties, this is not the case. If field-effect transistors are used, an inherently higher mismatch in threshold levels, usually referred to as .DELTA.V.sub.t, can lead to ambiguity in the states of the comparators, and resultant unreliability of the device.
An alternative approach for obtaining high resolution in parallel analog-to-digital converters is to use cascaded stages of smaller parallel converters. For example, a first four-bit converter could be used to quantize the analog input signal into one of sixteen levels, and a second four-bit converter used to provide a further four bits of resolution. Although this approach reduces the complexity of the overall conversion system, the two separate conversions result in a greater time delay, and necessitate the use of additional components, including a sample-and-hold circuit and a digital-to-analog conversion circuit.
It is an object of the present invention to provide a parallel analog-to-digital converter with a resolution of at least five bits, which avoids all of the aforementioned disadvantages and thereby provides a practical, high resolution, high speed converter.